Modern synchronous chips use large clock distribution networks spread over a die to distribute a clock to hundreds of thousands of elements. It is desirable for these elements, such logic and memory modules, to be substantially synchronized with one another. Thus, the relative arrival time difference between clock signals at the leaf nodes of a distribution network, the clock skew, directly impacts the timing margins of the chip. Elaborate care is taken to design these distribution networks to minimize clock skew. However, random within-die variations, along with other systematic variations still introduce a residual clock skew in the network.
As clock skew increases, the viable clock speed of the computer chip is reduced, thus also reducing the potential performance of the computer chip. On the other hand, as clock skew decreases, the viable clock speed of the computer chip is increased, thus also increasing the potential performance of the computer chip. Accordingly, it is desirable to reduce clock skew as much as practically possible.
Furthermore, at higher clock frequencies, the sensitivity of the computer chip to clock skew increases. For instance, a clock skew that is acceptable for a computer chip operating at a clock speed of few megahertz may be prohibitively large for a computer chip operating at a clock speed of a few gigahertz. As modern computer chips can operate at clock frequencies in the gigahertz range and higher, the importance of addressing clock skew increases.
Hence, a technique to measure the relative skew between two arbitrary leaf nodes of a clock network will be of great value in studying and characterizing clock skews, as well as potentially enabling a closed loop design of a clock network to reduce clock skew.
Techniques to measure skew between two signals are used in Phase Lock Loops (PLL), Delay Lock Loops (DLL) and Time-to-Digital Converters. PLLs and DLLs use a phase detector followed by a filter which gives a measure of the relative skew between two periodic signals. Time-to-digital converters which multiply time residue for improving the timing resolution have also been proposed.
However, these techniques may be difficult to use to measure the clock skew between two leaf nodes with arbitrary physical separation. This is because it becomes difficult to route these signals from the leaf nodes of the network to a common measurement location without adding yet more skew that corrupts the measurement. Alternative techniques like the PICA method or SEM imaging can be used to measure the clock skew of arbitrary leaf nodes. However these sophisticated techniques require extensive physical modification of the die and package, and are very expensive to use on a large scale.
Accordingly, it is desirable to develop new methods and systems that facilitate low-impact but accurate measurement of clock skew between arbitrary elements.